/*
 * (C) Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Author: Gilles Talis <gilles.talis@freescale.com>
 */

#ifndef __DMACHMUX_SAC58R_H__
#define __DMACHMUX_SAC58R_H__

#include <asm/imx-common/dmachmux.h>

/* DMA Channel sources */
enum {
	/* DMA request sources - DMA0(MUX0)/DMA1(MUX3) */
	SAC58R_DMAREQSRC_UART0_RX = 2,
	SAC58R_DMAREQSRC_UART0_TX = 3,
	SAC58R_DMAREQSRC_UART1_RX = 4,
	SAC58R_DMAREQSRC_UART1_TX = 5,
	SAC58R_DMAREQSRC_UART2_RX = 6,
	SAC58R_DMAREQSRC_UART2_TX = 7,
	SAC58R_DMAREQSRC_UART3_RX = 8,
	SAC58R_DMAREQSRC_UART3_TX = 9,
	SAC58R_DMAREQSRC_ESAI1_BFIFO_TX = 10,
	SAC58R_DMAREQSRC_ESAI1_BFIFO_RX = 11,
	SAC58R_DMAREQSRC_SPI0_RX = 12,
	SAC58R_DMAREQSRC_SPI0_TX = 13,
	SAC58R_DMAREQSRC_SPI1_RX = 14,
	SAC58R_DMAREQSRC_SPI1_TX = 15,
	SAC58R_DMAREQSRC_SAI0_RX = 16,
	SAC58R_DMAREQSRC_SAI0_TX = 17,
	SAC58R_DMAREQSRC_SAI1_RX = 18,
	SAC58R_DMAREQSRC_SAI1_TX = 19,
	SAC58R_DMAREQSRC_SAI2_RX = 20,
	SAC58R_DMAREQSRC_PDB 	= 22,
	SAC58R_DMAREQSRC_ENET_1588_CH2 	= 22,
	SAC58R_DMAREQSRC_FTM0_CH0 = 24,
	SAC58R_DMAREQSRC_FTM0_CH1 = 25,
	SAC58R_DMAREQSRC_FTM0_CH2 = 26,
	SAC58R_DMAREQSRC_FTM0_CH3 = 27,
	SAC58R_DMAREQSRC_USDHC0 = 28,
	SAC58R_DMAREQSRC_USDHC1 = 29,
	SAC58R_DMAREQSRC_ENET_1588_CH0 = 30,
	SAC58R_DMAREQSRC_ENET_1588_CH1 = 31,
	SAC58R_DMAREQSRC_FTM1_CH0 = 32,
	SAC58R_DMAREQSRC_FTM1_CH1 = 33,
	SAC58R_DMAREQSRC_ADC0 	= 32,
	SAC58R_DMAREQSRC_ASRC1_1 = 34,
	SAC58R_DMAREQSRC_ASRC1_2 = 35,
	SAC58R_DMAREQSRC_ASRC1_3 = 36,
	SAC58R_DMAREQSRC_ASRC1_4 = 37,
	SAC58R_DMAREQSRC_PORTA 	= 38,
	SAC58R_DMAREQSRC_PORTB 	= 39,
	SAC58R_DMAREQSRC_PORTC 	= 40,
	SAC58R_DMAREQSRC_PORTD 	= 41,
	SAC58R_DMAREQSRC_PORTE 	= 42,
	SAC58R_DMAREQSRC_ASRC1_5	= 43,
	SAC58R_DMAREQSRC_ASRC1_6	= 44,
	SAC58R_DMAREQSRC_RLE_RX	= 45,
	SAC58R_DMAREQSRC_RLE_TX	= 46,
	SAC58R_DMAREQSRC_SPDIF0_RX = 47,
	SAC58R_DMAREQSRC_SPDIF0_TX = 48,
	SAC58R_DMAREQSRC_USDHC2 = 49,
	SAC58R_DMAREQSRC_I2C0_RX = 50,
	SAC58R_DMAREQSRC_I2C0_TX = 51,
	SAC58R_DMAREQSRC_I2C1_RX = 52,
	SAC58R_DMAREQSRC_I2C1_TX = 53,

	/* DMA request sources - DMA1(MUX2)/DMA0(MUX1) */
	SAC58R_DMAREQSRC_UART4_RX = 2,
	SAC58R_DMAREQSRC_UART4_TX = 3,
	SAC58R_DMAREQSRC_UART5_RX = 4,
	SAC58R_DMAREQSRC_UART5_TX = 5,
	SAC58R_DMAREQSRC_SPDIF1_RX = 6,
	SAC58R_DMAREQSRC_SPDIF1_TX = 7,
	SAC58R_DMAREQSRC_SAI3_RX = 8,
	SAC58R_DMAREQSRC_PORTF = 10,
	SAC58R_DMAREQSRC_PORTG = 11,
	SAC58R_DMAREQSRC_PORTH = 12,
	SAC58R_DMAREQSRC_PORTJ = 13,
	SAC58R_DMAREQSRC_VSPA_GPO11_16 = 15,
	SAC58R_DMAREQSRC_VSPA_GPO11_17 = 16,
	SAC58R_DMAREQSRC_PORTK = 17,
	SAC58R_DMAREQSRC_PORTL = 18,
	SAC58R_DMAREQSRC_FECA_VITERBI_CMPLT = 19,
	SAC58R_DMAREQSRC_FECA_TURBO_CODE_CMPLT = 20,
	SAC58R_DMAREQSRC_FECA_REED_SOLOMON_CMPLT = 21,
	SAC58R_DMAREQSRC_FECA_DESCR_CMPLT = 22,
	SAC58R_DMAREQSRC_ENET_1588_CH3 = 23,
	SAC58R_DMAREQSRC_SAI4_RX = 24,
	SAC58R_DMAREQSRC_SAI5_RX = 25,
	SAC58R_DMAREQSRC_SAI6_TX = 26,
	SAC58R_DMAREQSRC_SAI6_RX = 27,
	SAC58R_DMAREQSRC_SAI7_TX = 28,
	SAC58R_DMAREQSRC_FTM0_CH4 = 30,
	SAC58R_DMAREQSRC_FTM0_CH5 = 31,
	SAC58R_DMAREQSRC_FTM0_CH6 = 32,
	SAC58R_DMAREQSRC_FTM0_CH7 = 33,
	SAC58R_DMAREQSRC_ESAI0_BFIFO_TX = 34,
	SAC58R_DMAREQSRC_ESAI0_BFIFO_RX = 35,
	SAC58R_DMAREQSRC_I2C2_RX = 36,
	SAC58R_DMAREQSRC_I2C2_TX = 37,
	SAC58R_DMAREQSRC_I2C3_RX = 38,
	SAC58R_DMAREQSRC_I2C4_TX = 39,
	SAC58R_DMAREQSRC_ASRC0_1 = 40,
	SAC58R_DMAREQSRC_ASRC0_4 = 41,
	SAC58R_DMAREQSRC_ASRC0_2 = 42,
	SAC58R_DMAREQSRC_ASRC0_5 = 43,
	SAC58R_DMAREQSRC_QSPIO_RX = 44,
	SAC58R_DMAREQSRC_QSPIO_TX = 45,
	SAC58R_DMAREQSRC_FLEXCAN0 = 46,
	SAC58R_DMAREQSRC_FLEXCAN1 = 48,
	SAC58R_DMAREQSRC_FLEXCAN2 = 50,
	SAC58R_DMAREQSRC_ASRC0_3 	= 52,
	SAC58R_DMAREQSRC_ASRC0_6 	= 53,
};


#endif	/* __IOMUX_SAC58R_H__ */
